In a typical metal-oxide semiconductor (MOS) transistor, one of a source region and a drain region is formed in a reverse conducting well that forms a device region. In such a configuration, the source region or the drain region is isolated by a p-n junction from the well formed at an interface between the source region and the well or between the drain region and the well.
However, in the typical MOS transistor, an operating speed may be reduced due to a parasitic capacitance of the p-n junction and current leakage may be easily generated.
Thus, there is proposed a metal-oxide-semiconductor (MOS) transistor structure in which wells are separated by an insulator structure such as oxide films, nitride films or voids that are locally formed beneath the source region or the drain region in the device region. Such a MOS transistor structure may be capable of reducing the junction capacitance or reducing the leakage of current.
Japanese Laid-open Patent Publication No. 2009-10040 disposes an example of a process for forming the MOS transistor structure. The disclosed process for forming the MOS transistor structure includes forming a layered structure having a SiGe mixed crystal layer and a Si layer on the SiGe mixed crystal layer, and removing the SiGe mixed crystal layer alone utilizing the etching rate difference between the Si layer and the SiGe mixed crystal layer. Silicon oxide film embedded regions may be locally formed immediately beneath the source region or the drain region by filing the voids after the SiGe mixed crystal layer has been removed, and hence, the silicon-on-insulator (SOI) structure may be formed locally.